Skill: cadence allegro , emi / emc , hardware , hdl , signal integrity , dft , rf , pcb layout , gerber; Exp: 2-3 years; In this position, the candidate will be responsible for design of soft IP cores for Intel’s next generation chips (including SOCs) for the different market segments. Design Lead will be responsible for the execution and quality of at least 2 IPs and will sign off all design checks and interact with SOC for all integration issues Qualifications Master of Science (or a Master of Technology) degree in Electrical Engineering with more than ten years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than twelve years of relevant industry experience. Inside this Business Group Legal Disclaimer Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status. It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.
Function: IT Hardware : Hardware Products & Services