Sr Design Engineering Manager


  • Company:
    Cadence Design Systems India Pvt Ltd
  • Location:
  • Salary:
    negotiable / month
  • Job type:
    Full-Time
  • Posted:
    1 month ago
  • Category:
    Telecom | IT-Hardware/Networking

Skill: physical design , static timing analysis , soc , rtl design , formal verification , drc , verification , lvs , asic design , physical verification , floor planning , signal integrity , dft; Exp: 0-3 years; At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You will work with an elite team of physical design implementation engineers and have personal design responsibility, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management. An opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. Responsibility includes participating in or leading next generation physical design, methodology and flow development in advanced technology nodes Working closely with RTL design team & Analog Team to ensure successful tapeouts. This is definitely not just another physical design job , This is Cadence IPG , the fastest growing business unit in Cadence. This is where the best IP in the industry is created for now and the future. In a short years ,we have become one of the leading provider of IP’s worldwide. Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills. B.Tech/BE/ME/Mtech with hands-on experience in physical design and verification. Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus,Tempus, PVS, Voltus. Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl. Were doing work that matters. Help us solve what others cant.

Hardware Design

Degree: ME/ M.Tech./ MS (Engg/ Sciences)

Experience: 0-3

Function: IT Hardware : Hardware Products & Services