SENIOR ENGINEER (39121)

  • Company:
    Aricent Technologies ( Holdings ) Ltd
  • Location:
  • Salary:
    negotiable / month
  • Job type:
    Full-Time
  • Posted:
    1 week ago
  • Category:
    IT-Hardware/Networking | Telecom

Skill: physical design , static timing analysis , lvs , icc , physical verification , floor planning , signal integrity , drc , synopsys; Exp: 2-3 years; Career Opportunities SENIOR ENGINEER (39121) Req ID39121-Posted28/06/2018-Noida-Noida 1.Should be able to handle a block of Medium/High complexity 2. Should be an Independent Performer 3.Ability to communicate effectively with multiple global cross-functional teams. 4. Enthusiastic and ability to be an independent player and also work in teams with positive attitude 3.Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. 5. Solutions orientation; Quality driven; Execution minded; Customer focused MandatorySkills 1.Strong Back ground of ASIC Physical Design Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure 2.Extensive experience and detailed knowledge in Cadence or Synopsys physical Design Tools. 3.Expertise in scripting languages such as PERL, TCL 4.Strong Physical Verification skill set. 5.Static Timing Analysis in Primetime or Primetime-SI 6.DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off experience 7.Experience using Synopsys ICC Tool and tape-out experience of multiple complex chips at 14 nm or below 8.Experience with Mentor Calibre or Synopsys ICC and ICV 9.Proficient in planning for and addressing electrical considerations throughout the design process (EM, IR, Noise, etc.) 10.Physical verification flow automation exposure will be an added advantage 11.Expertise in STA tools (Primetime) and flow. 12.Knowledge of timing corners/modes, process variations and signal integrity related issues. 13. experience in timing/SDC constraints generation and management. 8.Experience with Mentor Calibre or Synopsys ICC and ICV 9.Proficient in planning for and addressing electrical considerations throughout the design process (EM, IR, Noise, etc.) 10.Physical verification flow automation exposure will be an added advantage 11.Expertise in STA tools (Primetime) and flow. 12.Knowledge of timing corners/modes, process variations and signal integrity related issues. 13. experience in timing/SDC constraints generation and management. Experience (In Month) 84 Qualification BE M.Tech

Hardware Design

Degree: ME/ M.Tech./ MS (Engg/ Sciences)

Experience: 2-3

Function: IT Hardware : Hardware Products & Services