Skill: soc , atpg , silicon validation , rtl design , design compiler , system verilog , verification , ovm , schematic , verilog , dft , synopsys; Exp: 0-3 years; Senior DFT Lead Job Description As a manager, set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance. Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Selects, develops, and evaluates SoC design engineers to ensure the efficient operation of the function. n this position, you will be responsible for design and validation of various DFT features such as Scan, MBIST, JTAG, BScan, analog DFT, etc. for Intel’s leading edge SoC designs. You will work with post-silicon teams to comprehend their usage models, test time/fault coverage/data collection goals, and tester capabilities and limitations. You will work with IP and integration design teams to understand the design and functional-mode behaviors of the logic and circuits. You will micro-architect DFT features which are compatible with the specific product/post-silicon requirements and constraints. You will assist in the RTL and schematic implementation and pre-silicon validation and debug of these DFT features. You will also be expected to deliver high-quality documentation for consumption by the post-silicon teams who will use the DFT features. Strong knowledge of DFT architectures & methodologies. This includes Scan, ATPG, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan, etc. Proven knowledge of Verilog & System Verilog, RTL design and micro-architecture skills. Strong knowledge of SoC tools/methodology (OVM, Saola, ACE, VCS*, Lintra, CDC, Synthesis, Spyglass, Tessent ATPG/MBIST tools, Synopsys ATPG tools, design compiler, etc). Strong debug skills and demonstrated experiences in Perl & TCL scripting. Strong Si debug skills, ATE requirements and understanding of volume test requirements. Strong Communications skills and the ability to effectively work with cross functional teams. Qualifications BTech, MTech, BE, in Electorics & Communication, Digital Electronics, Electronics & Electrical Inside this Business Group Legal Disclaimer Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status. It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.
Function: IT Hardware : Hardware Products & Services