Physical Design Specialist/Lead (Custom HM Implementation)

  • Company:
    Qualcomm Inc
  • Location:
  • Salary:
    negotiable / month
  • Job type:
  • Posted:
    4 weeks ago
  • Category:
    IT-Hardware/Networking | Telecom

Skill: physical design , static timing analysis , soc , design verification , rtl design , design compiler , drc , system verilog , verification , hardware , rtl compiler , cmos , hspice , hardware engineering , schematic , verilog , floor planning , dft , synopsys , circuit design; Exp: 2-5 years; Job Overview *Candidate will be part of CSI team working on RTL- GDS HM implementations using custom flow and methodology for CSI IPs . *Qualcomm is one of the fastest growing semiconductor organization in India making high-end Chips with the most advanced technologies. To support its growing needs, we have strong CSI team for the design, development of various highspeed and low power IPs being used in SoC. Individual has to work on RTL-GDS implementation. This will involve innovating new solutions in close collaboration with the other design teams. Job Responsibilities Job responsibilities include design and development of custom macro using Schematic design /synthesis Frontend verification and model generations Physical design using Innovus/Icc2 Timing Signoff and PV Candidate should be able to collaborate with different teams. Minimum Qualifications Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field. 2 years Hardware Engineering experience or related work experience. Preferred Qualifications Strong knowledge in transistor circuit design& block level logic design of Memory subsystem & Data path. STA for the design to close Set-up, Hold, MPW, Transition, etc Design verification using ESPCV & LEC, Simulation using Finesim & HSPICE. Front-end RTL Design (Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler, LEC, PLDRC, Static Timing Analysis and PTPX) Physical Design using industry-standard RTL2GDS flow including Synopsys ICC2, Cadence Encounter. Scripting in Perl/Python/Shell/Tcl for productivity is a plus IP development (custom macro transistor level design, physical integration, collateral generation, flow development) and PPA quantification. Interface with Process Technology Team to understand the complex DRC and DFM requirements of the advanced technology nodes Work with cross functional teams (Architecture, Test/Verification , Product, CAD, Layout, Physical Design) to gather/define/implement specs Transistor level implementation of the block using CMOS/Domino/Cell-Based/Data path styles Implement power/clock gating techniques, Implement power/clock gating techniques, Implement industry standard as well as custom DFT techniques Implement clock distribution using custom/CTS techniques for low skew/latency/power, Implement block layout using custom/compiler techniques using custom/semi-custom/stdcell libraries Implement block level floor planning using custom and/or tiling techniques Education Requirements Required Bachelor’s, Electrical Engineering Keywords

Hardware Design


Experience: 2-5

Function: IT Hardware : Hardware Products & Services