Skill: physical design , static timing analysis , soc , design compiler , drc , lvs , physical verification , synopsys; Exp: 8-10 years; JOB DESCRIPTION SUMMARY Will be working closely with Physical design team understanding new physical design methologies. Performing Place & route, IR drop analysis, Physical Verification. Should have worked on full chip level. And handled multiple projects technically JOB DESCRIPTION Experience 8 to 10 Years Job Location Hyderabad Skills requried Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes, also worked on Place & Route, Physical Verification (DRC/LVS/Antenna). Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency Must have worked on experience with Synopsys/Mentor suite (IC Compiler, Primetime, Design Compiler, IC Validator, Calibre) Strong experience on Static Timing Analysis (PrimeTime), EM/IR-Drop/Cross-talk analysis (PT-SI, Apache), formal or Physical Verification (Formality, Calibre) Understanding the practical application of methodologies and Physical Design Tools, Flow Automation and Improvements Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques.
Function: IT Hardware : Hardware Products & Services