Assistant Project Manager

  • Company:
    Cyient Ltd
  • Location:
  • Salary:
    negotiable / month
  • Job type:
    Full-Time
  • Posted:
    5 days ago
  • Category:
    IT-Hardware/Networking | Telecom

Skill: soc , rtl design , axi , ahb , system verilog , verification , asic verification , ovm , uvm; Exp: 4-7 years; Job Role Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level Develop IP level/SoC level test plans based on the design/architectural specs. Coverage Analysis and Coding Run simulations & regressions, debug test failures to identify test case issues & RTL design issues Define and develop block/full chip level verification environment and its components Required Skill 4 years of experience in ASIC Verification and Methodologies Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies Good understanding of RTL concepts Good understanding of AHB/AXI protocol Expertise in PCI-e/USB/Ethernet/Switch protocol is an added advantage Knowledge of Perl/TCL is Must Good communication skill JOB DESCRIPTION Job Role Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level Develop IP level/SoC level test plans based on the design/architectural specs. Coverage Analysis and Coding Run simulations & regressions, debug test failures to identify test case issues & RTL design issues Define and develop block/full chip level verification environment and its components Required Skill 4 years of experience in ASIC Verification and Methodologies Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies Good understanding of RTL concepts Good understanding of AHB/AXI protocol Expertise in PCI-e/USB/Ethernet/Switch protocol is an added advantage Knowledge of Perl/TCL is Must Good communication skill

Hardware Design

Degree: 

Experience: 4-7

Function: IT Hardware : Hardware Products & Services